“It’s enough for Intel to show that there was a known problem of cache coherency in the art, that Bauman’s secondary cache helped address that issue, and that combining the teachings of Kabemoto and Bauman wasn’t beyond the skill of an ordinary artisan.” – Judge Sharon Prost
On March 13, the U.S. Court of Appeals for the Federal Circuit (CAFC) issued a precedential decision in Intel Corp. v. PACT XPP Schweiz AG reversing a final written decision of the Patent Trial and Appeal Board (PTAB) that found Intel had failed to show that PACT’s patent claims were invalid for obviousness. In reversing, the Federal Circuit ruled that the PTAB improperly rejected Intel’s “known technique” rationale supporting a motivation to combine prior art references under the flexible analysis set out by the U.S. Supreme Court’s landmark 2007 obviousness ruling in KSR v. Teleflex.
Intel Challenges Patent Claims Covering Multiprocessor System Improving Cache Coherency
PACT owns U.S. Patent No. 9250908, Multi-Processor Bus and Cache Interconnection Systems. The ‘908 patent claims a multiprocessor system having a particular architecture designed to improve the coherency of data files stored on multiple cache memories, preventing inconsistencies that can arise if a processor changes a local data file and the change is not propagated to each cache memory. At issue on appeal was language from independent claim 4 of the ‘908 patent, which includes a claim limitation reciting an interconnect system “interconnecting… each of the separated cache segments with neighboring separated cache segments.”
After PACT asserted the ‘908 patent against Intel in several actions filed in the District of Delaware and the District of Northern California, Intel petitioned the PTAB for inter partes review (IPR) challenging the validity of PACT’s patent claims as obvious over the prior art. In a final written decision issued in August 2021, the PTAB rejected Intel’s arguments that prior art references contained a teaching, suggestion or motivation to combine and that the combination of two prior art references represented the use of known techniques to improve similar devices in the same way.
Intel had asserted a pair of prior art references during the IPR proceedings, and the Federal Circuit’s decision noted that, during the IPR proceedings, PACT did not dispute that the combination of those references taught each limitation of claim 4. Those prior art references included a U.S. patent claiming a processor system that uses a “snooping” system along a shared bus to maintain cache coherency (“Kabemoto”) and another U.S. patent claiming a multiprocessor data processing system designed to maintain cache coherency by utilizing a global, segmented secondary cache (“Bauman”).
CAFC: Known Technique Need Only Be a Suitable Option to Satisfy KSR’s Analysis
During the IPR proceedings at the PTAB, Intel had argued that a person of ordinary skill in the art would be motivated to combine the known technique of Bauman’s global second-level cache with the internal snoop bus of Kabemoto, meeting the limitations of the ‘908 patent’s claimed interconnect system. In rejecting Intel’s “known techniques” rationale, the PTAB found that a person of ordinary skill would not regard Bauman’s technique as an obvious improvement to Kabemoto because Kabemoto already addresses the cache coherency issue with a technique similar to Bauman’s teaching.
As the Federal Circuit held in its decision issued this week, the PTAB’s reasoning on this point belied its own conclusion that the known techniques rationale did not present a motivation to combine Bauman and Kabemoto. “That Kabemoto and Bauman address the same problem and that Bauman’s cache was a known way to address that problem is precisely the reason that there’s a motivation to combine under KSR and our precedent,” reads the Federal Circuit panel decision authored by Circuit Judge Sharon Prost. The Federal Circuit did not address Intel’s arguments on the teaching, suggestion or motivation to combine present in either Kabemoto or Bauman as the known techniques rationale was sufficient for reversal.
Under KSR and its progeny, the motivation to combine analysis is flexible enough that “any need or problem known in the field of endeavor at the time of invention and addressed by the patent” can provide the required motivation. Since KSR, the Federal Circuit has since found that “universal” motivations to improve technology within a particular field can provide a motivation to combine “even absent any hint of suggestion in the references themselves,” language emphasized by the Federal Circuit’s 2021 ruling in Intel v. Qualcomm. According to the Federal Circuit, these cases establish that a motivation to combine exists if there is a known technique to address a known problem using prior art elements according to their established functions. “And we specify address a known problem because ‘[i]t’s not necessary to show that a combination is the best option, only that it be a suitable option,’” Judge Prost wrote, citing language from Intel.
“It’s enough for Intel to show that there was a known problem of cache coherency in the art, that Bauman’s secondary cache helped address that issue, and that combining the teachings of Kabemoto and Bauman wasn’t beyond the skill of an ordinary artisan. Nothing more is required to show a motivation to combine under KSR, so we reverse the Board’s finding to the contrary.”
Remand to PTAB to Address Remaining Patentability Disputes on Claim 5
The Federal Circuit also reversed the PTAB’s determination that Bauman did not teach the segment-to-segment limitation recited by claim 4 of PACT’s ‘908 patent. The appellate court found that Figure 6 of Bauman “teaches–if not plainly illustrates” the claimed segment-to-segment limitation. “That was Intel and PACT’s understanding at the Board, and that’s our understanding from the record on appeal,” Judge Prost wrote. “We can discern no other reasonable understanding of this figure.”
While the Federal Circuit reversed both factual findings appealed from the PTAB by Intel, the appellate court remanded the case back to the PTAB to address any patentability disputes regarding claim 5 of the ‘908 patent. While the validity of claim 4’s language was at issue in the Federal Circuit appeal, the IPR proceedings focus on claim 5 of the ‘908 patent, which claims the processor system of claim 4 with an arbiter that is operable to allow a processor to access the interconnect system in a chronological sequence.